FAQ

Frequently Asked Questions

QPU Data

What's the 1Q/2Q native gate set?

The authoritative source of this information is the Quil calibration program, which can be retrieved directly from the API or via utilities in pyQuil and other QCS tools.

If there's a DEFCAL for a gate, it's native; if not, you'll have to replace it prior to translation and execution. Note that:

• This native gate set changes over time

• A given gate may not be available on all qubits or edges within the topology of a QPU

What are the 1Q/2Q gate times?

Like the native gate set, the source of truth for this information is the Quil calibration program. Because the calibrations are shown for all native gates, the duration of a calibrated gate can be computed from the Quil implementation.

The gate time can usually be computed by hand, especially for simple gates. However, Quil utilities in Rust and Python can compute individual gate durations as well as the schedule of gates within an overall program. See the linked docs for examples.

What are the 1Q/2Q operation fidelities?

This data is present within the instruction set architecture document available from the QCS API.

What is the current T1, T2, or other benchmark?

Some benchmarks are available within the instruction set architecture document. However, some are left to the user to compute. For example, for practical reasons, we do not regularly publish T1 and T2 values for Ankaa QPUs.

Does Ankaa support active reset?

As of May 2024, Ankaa QPUs support only passive reset. Active reset support arrives in mid-2024.